1. Field of the Invention
The present invention relates to a method of decoding an audio signal included in a Digital Video (DV) data stream. The DV format is commonly used to store video and audio sourced from domestic camcorders. The data format is adapted to store both data related to the video signal and the audio signal. Both signals are generally decoded separately.
2. Description of the Prior Art
The audio part of DV data is formatted to include:                Audio Pre-amble        14 Data-Sync blocks, each including:                    a Sync area of 2 bytes            an ID code of 3 bytes            a data area of 85 bytes                        Audio Post-amble        
The format of the data-sync blocks is shown in FIG. 1.
When the audio data is encoded and stored in DV format, audio samples and data are shuffled over different tracks and data-sync blocks within an audio frame. Firstly, audio data is shuffled, and then dummy data is added. The position of the nth audio sample is determined from the equations (1)-(6) which follow:
  {                                                             t              1                        =                                          [                                                      ⌊                                          n                      /                      3                                        ⌋                                    +                                      2                    *                                          (                                              n                        ⁢                        %3                                            )                                                                      ]                            ⁢              %              ⁢              T                                                            (                          CH              ⁢                                                          ⁢              1                        )                                                (            1            )                                                                          t              2                        =                                                            [                                                            ⌊                                              n                        /                        3                                            ⌋                                        +                                          2                      *                                              (                                                  n                          ⁢                          %3                                                )                                                                              ]                                ⁢                %                ⁢                T                            +              T                                                            (                          CH              ⁢                                                          ⁢              2                        )                                                (            2            )                                                                          s              1                        =                                          C                1                            +                              3                *                                  (                                      n                    ⁢                    %3                                    )                                            +                              ⌊                                                      (                                          n                      ⁢                      %                      ⁢                                              K                        1                                                              )                                    /                                      K                    2                                                  ⌋                                                                                                                          (            3            )                                                                          b              1                        =                                          C                2                            +                              B                *                                  ⌊                                      n                    /                                          K                      1                                                        ⌋                                                                                          (                          byte              ⁢                                                          ⁢              1                        )                                                (            4            )                                                                          b              1              ′                        =                                          C                2                            +              1              +                              B                *                                  ⌊                                      n                    /                                          K                      1                                                        ⌋                                                                                          (                          byte              ⁢                                                          ⁢              2                        )                                                (            5            )                                                                          b              1              ″                        =                                          C                2                            +              2              +                              B                *                                  ⌊                                      n                    /                                          K                      1                                                        ⌋                                                                                          (                          byte              ⁢                                                          ⁢              3              ⁢                                                          ⁢              for              ⁢                                                          ⁢              4              ⁢                              -                            ⁢              ch              ⁢                                                          ⁢              mode                        )                                                (            6            )                              
In relation to the above equations, R is the set of all real numbers, Z is the set of all integers (positive and negative), N is the set of all natural numbers, t1 and t2 are the track numbers for channel 1 and channel 2 respectively, s1 is the sync block number, and b1 is the byte position within the DIF block. A DIF (Digital Interface Frame) block is a sub-part of a DV frame. A DV frame includes either 90 or 108 DIF frames depending on whether the system is 525/60 or 625/50. FIG. 5 illustrates the relationship between a DV frame and a DIF block, where the dotted box represents a DV frame, while each individual row of data samples represents a DIF block.
With regard to the notation used in this specification, [a,b] indicates a range inclusive of both a and b; (a,b] indicates a range exclusive of a, but inclusive of b; and [a,b) indicates a range inclusive of a, but exclusive of b.
If x is a real number (xεR), then [x] indicates the largest integer that is ≦x, and x%y indicates the remainder of the division of x by y, where x, yεN. By number theory, x%yε[0,y).
It can be seen from equations (4)-(6) that bytes belonging to the same sample are distributed consecutively within the same DIF block. Samples from different channels but with the same indices have the same sync block number and byte position but different track numbers. The relationship between sync-blocks and tracks is illustrated in Table 1, which shows how they are related to the sample index and the constants T, K1, K2, and B.
The coding process involves a shuffling operation which maps from the PCM (Pulse Code Modulation) domain to the DV domain. FIG. 2 shows a top level block diagram of the mapping operation, showing how the raw PCM data is mapped on the basis of t1, t2, s1 and b1 into DV format. FIG. 3 shows a more detailed view of the shuffling of particular samples, in which the left hand side shows a PCM frame with data samples D0 . . . DN. The dotted rectangle on the right hand side shows a DV frame. For each PCM sample, Dn, its index, n, is used as the input to the shuffling equations (1) to (6) to determine its corresponding position in the DV frame. That is, (t1, s1, b1)=f(n)DV[t1][s1][b1]=PCM[n]=Dn.
The values T, B, K1 and K2 are system dependent and are summarized in the table below, along with the constants C1 and C2.
TABLE ISystemTK1K2BC1C22-ch525/60545152210mode625/506541822104-ch525/60545153210MODE625/50654183210
The numbers in the System column of the above table refer to the number of lines in the video system and the refresh rate. So, 525/60 is a 525 line TV system with a 60 Hz refresh rate.
The DV audio signal is decoded to enable the audio to be reproduced by playback equipment, such as a video cassette player. If the shuffled coded data may be represented as (t1, t2, s1, b1)=f(n), then the reverse mapping f−1 may be considered to provide the correct order of data. This concept is shown in FIG. 4.
However, this concept is not generally possible in practice, as the shuffling process involves modular and non-linear operations, such as └x┘, which result in a one-to-many reverse relationship. It is therefore not generally possible to easily find a suitable reverse mapping f−1.
Prior art DV audio decoders therefore generally operate in one of two known ways. The first way involves the creation of a Look Up Table (LUT) in which a mapping relationship between received data and the required output data is pre-computed and stored to enable the received data to be re-formatted accordingly.
This method includes the following steps:                Every element in the table is initialized to −I;        For every nε[0,N], computer (t1, s1, b1) using the shuffling equations (1)-(6);        Store values for n in a LUT with index [t1, s1, b1], i.e., LUT[t1][s1][b1]=n;        For any incoming shuffled data byte, determine its position in the raw PCM data:                    IF LUT[t1][s1][b1]=−1 THEN discard value,            ELSE PCM[LUT[t1][s1][b1]]=DV[t1][s1][b1]                        
The major disadvantage of this particular method is the large amount of memory required to store the LUT. Since the constants (T, K1, K2 and B) involved in the shuffling equations can be of different values depending on whether it is a 525/60 or 625/50 system, or a 2 or 4-channel system, four separate look-up tables are required. Each LUT is similar in size to a DV frame.
The second method involves receiving and buffering an entire DV audio frame, which is then analyzed so that the received data can be decoded on the basis of the analysis.
Using this method, there is no requirement to explicitly determine the reverse mapping f−1, but it has the drawback that an entire DV audio frame has to be buffered or stored before decoding can start. This is because a sample occurring in the very first position of the raw PCM data may be shuffled to a position very late in the DV frame. Therefore, this technique may only be used once a complete DV audio frame is available.
To use this method, values of (t1, s1, b1) are calculated for n=0 to N. i.e., (t1, s1, b1)=f(n). Then PCM[n]=DV[t1][s1][b1]
The prior art methods are problematic in that they both require relatively large amounts of memory in order to either store the LUT or buffer the received signal for further analysis. The methods themselves are relatively straightforward to implement, but the memory requirements render them undesirable in practical systems.